Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification

Abstract

BCH codes and cyclic redundancy check (CRC) are broadly used to ensure the reliability and integrity of data transmission. BCH encoders and CRC en/decoders are implemented by linear feedback shift registers (LFSRs). In prior LFSRs, the input is added to the most significant tap (MST), whose output is fed back and affects each of the other registers in the next clock cycle. The effects on the registers in a parallel design are translated to a pre-processing matrix multiplication, which may occupy the majority of the LFSR area. In this paper, we propose to add the input to the least significant tap (LST) and derive the corresponding parallel processing formula. Since the output of the LST is shifted to the MST before being fed back to the other taps, the corresponding pre-processing matrix is much simpler. Complexity reductions achievable by applying state-space transformations on LST-input LFSRs are evaluated and possible optimizations are discussed. For various CRCs considered, the proposed designs lead to 10–40% gate count reduction and significant power reduction compared to prior approaches with no or negligible penalty on the throughput.