High – Speed and Low Area-Efficient VLSI Architecture of Three-Operand Binary Adder

Abstract

Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three- operand addition. In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity. Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE 14.7