Abstract
The three-operand binary adder is a fundamental component in cryptography and pseudorandom bit generators (PRBGs). The carry-save adder (CS3A) is a popular method for performing three-operand addition. In the final stage of the carry saving adder, the ripple-carry adder is used, resulting in a significant critical path delay. For three-operand addition, other adder like Han-Carlson adder (HCA) can be employed, which greatly reduces the delay, but area will increase. Hence, a new high-speed and area-efficient three-operand binary adder is designed, which uses pre-computation logic and carry prefix calculation logic for designing three-operand binary adder with less time and area. In comparison with the previous adders such as the carry-save adder and the Han-Carlson adder, the proposed adder uses less space and time. Xilinx ISE 14.7 tool is used to verify the synthesis and simulation.
Published Version
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