High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs

Abstract

For fully-depleted SOI MOSFETs, fabricated in standard and strained 65 nm technologies, it is observed that the drain current I normalized for the device length L and width W levels off at sufficiently high gate voltage overdrives. Also the normalized drain current 1/ f noise spectral density S I shows a plateau value for high front gate voltages. For both strained and non-strained devices there exists a relation between the two plateau values and a y ∼ ( x) 1/4 law is found for the experimental data where x = S I plateau ( L 3 / WN ot ) , y = I plateau ( L/t W), S I plateau and I plateau are the plateau values of S I and I, respectively, and N ot is the density of the oxide traps responsible for the 1/ f noise observed. Compared to standard SOI the use of strained SOI (sSOI) increases the magnitude of the plateau and makes its dependence on the device geometry more pronounced, while the impact of a strained contact etch stop layer (sCESL) is limited. The experimental observations are explained by taking into consideration the field and geometry dependence of the mobility and the influence of negative oxide charges on the drain current.