Study for high voltage gate RIE process in LDI (LCD driver IC) device fabrication

Abstract

In this study, we reported on the evaluation result of the optimized high voltage gate patterning in liquid crystal display (LCD) driver integrated circuit (IC) with its preparation, characterization and composition of each parameter such as etching gas chemistry, RF power, and pressure. The patterning process of high voltage gate oxide was performed with the CF 4 /CHF 3 /O 2 /Ar based gas chemistry to avoid the leakage current from high voltage gate stack by non-uniform remnant gate oxide thickness. Albeit we obtained the minimized fluctuation of gate oxide thickness, the plasma damage by plasma patterning process affected the leakage current of high voltage gate film stack. In conclusion, we found that the major parameter for leakage current in high voltage gate stack by DOE method of gate patterning and achieved that the optimized condition of high voltage gate patterning. To optimize the performance of high voltage gate oxide, the thickness of remnant oxide must be controlled uniformly in gate patterning for improving the margin of high voltage gate transistor. Verifying that the patterning performance of physical and electrical characteristics with analytical tools such as secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), auger electron spectroscopy (AES) and probe station as well.