Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

Abstract

ABSTRACTThe electrical behavior of decananometer MOS transistors with high-k dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-k materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code.