Trap density in Ge-on-Si pMOSFETs with Si intermediate layers

Abstract

The 1/f noise of three different Ge channel p-type MOSFETs, epitaxially grown on silicon substrates was measured between 1 and 100 Hz. The difference between the p-MOSFETs is the thickness of the interfacial Si layer between Ge channel and gate stack that is needed to passivate the Ge channel. The gate stack consists of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TaN/TiN layers. Noise in all structures complies with the McWorther carrier number fluctuation model. The magnitude of the noise power spectral density of the drain current was found to increase with decreasing Si interfacial layer thickness. The extracted trap densities are between 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . These values are currently at the lower end of the range of other MOSFETs with high-k dielectric gate stacks.