Electrical characterization and reliability of double-doped drain MOS transistors compatible with an EEPROM process

Abstract

Abstract Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manufactured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at V ds = 10 V , V gs = 5 V . The observed degradation seems to be mainly due to acceptor-type interface state creation near the drain junction.