Hot-Carrier Degradation and Electric Field and Electron Concentration near Drain Junction in Low-Temperature N-Channel Single Drain and Lightly Doped Drain Polycrystalline Silicon Thin Film Transistors

Abstract

We proposed a two-dimensional (2-D) physical model of n-channel polycrystalline silicon (poly-Si) single drain (SD) and lightly-doped drain (LDD) thin film transistor (TFT) to analyze hot-carrier degradation. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate, and the current flows in the deep channel region near the drain junction. In poly-Si n-channel TFTs, it was predicted from our 2-D device simulation that the generation of both band-tail states in poly-Si and interface states at both interfaces can contribute to hot-carrier degradation. We have shown that, in the case of n-channel SD TFTs, generated band-tail states greatly affect drain avalanche hot-carrier (DAHC) degradation for longer stress time of 10,000 s.