Abstract
Two-step heat-treated silicon wafers have been used to determine the electrical activity of bulk stacking faults. These wafers have been processed in two different facilities to minimize the possibility that the results might depend on impurities incorporated during wafer processing. DLTS measurements show a dominant energy level at E c − E t = 0.48 ± 0.05 eV due to oxygen-induced stacking faults. Trap concentrations have been correlated to optically detectable bulk stacking faults when the size of the stacking faults is more than 1 μn. Our results show the size and density of the stacking faults are related to the observed electrical activity of the microdefects.
Published Version
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