Electrically Active Stacking Faults in Silicon

Abstract

The influence of oxidation induced stacking faults on the electrical characteristics of p‐n junctions in silicon has been studied by employing scanning and transmission electron microscopy in conjunction with electrical measurements. Diodes were fabricated with a junction depth and an integrated boron concentration of ohm‐cm n‐type epitaxial silicon.The presence of decorated stacking faults in the field region of the diodes examined is found to introduce excess reverse leakage currents in the junction. However not all faults introduce the same degree of leakage and the electrical activity of the faults is found to vary. The concept of the “threshold voltage” of a stacking fault is introduced which is a measure of the specific electrical activity of the fault. Electrically active faults introduce excess reverse currents in the diodes which are characterized by a relationship between the reverse log ratio measured at low voltages and the characteristic “threshold voltage” of the faults. The electrical activity is related to both the size and the structure of the faults. The smaller faults which are also more prone to impurity decoration are electrically more active than larger faults which are decorated to a lesser degree. Models are presented to account for the electrical activity of the faults. These models are based on the strain effects of the decorated faults and on the distortions produced in the p‐n junctions by the presence of faults.