Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Abstract

Gate-induced drain leakage (GIDL) has become a crucial factor of determining current characteristics in ultra-small devices where the junction doping concentration is abruptly graded. It should be effectively suppressed for the low standby power operation (LSTP) of highly scaled metal–oxide–semiconductor field effect transistor (MOSFET) devices. In this work, the effects of doping profile on GIDL current are thoroughly investigated. In order to adjust the doping profile, we set up two variables: peak-to-gate edge distance and doping gradient. Underlap length can be also determined by the difference of these two variables. Based on analyses of the combinational effects of peak-to-gate distance and doping gradient, the methods of minimizing GIDL are searched for LSTP operation of silicon (SOI) FinFET on 32 nm technology node. The effective suppression of GIDL current can be achived by a number of combinations made by those two variables, rather than by a unique solution. 2-D and 3-D maps plotting the permissible pairs of variables will be given as the results by numerical simulations. Also, on the way to the aim, a quantitative method of extracting GIDL will be also introduced, which is more physically reasonable compared with existing one.