Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor

Abstract

Recently, gate-induced drain leakage (GIDL) has become a crucial factor of current characteristics as junction doping concentration becomes more abruptly graded owing to device scaling. It should be effectively suppressed for the low-standby-power operation of ultra small metal–oxide–semiconductor field effect transistor (MOSFET) devices. In this work, the appropriate underlap length range for the effective minimization of GIDL in 20-nm-level four-terminal (4-T) fin-shaped FET (FinFET) on silicon-on-insulator (SOI) is established. In order to identify the effect of underlap length on GIDL more precisely, the source and drain (S/D) junction doping profile and the majority/minority carrier lifetimes have been extracted by the measurement of a p–n junction test element group (TEG). The TEG was fabricated under the same process conditions that were used in forming the S/D junctions of 100-nm-level 4-T SOI FinFET in our previous research. The GIDL component in the off-state current is investigated with underlap length variation along with the inspection of basic current characteristics. For low-standby-power operation, an underlap junction is more desirable than an overlap junction, and the underlap length should be at least 10 nm to suppress GIDL effectively.