Abstract
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-㎚ node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-㎚ channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 ㎚ to suppress GIDL effectively for reliable low standby power (LSTP) operation.
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