Design of Micro-sensors for Measuring Localised Stresses during Fan-Out Wafer Level Packaging (FOWLP) Processes

Abstract

Though an understanding on the development of stresses in Si devices after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer level packaging processes. In this paper, the micro-stress sensors have been designed, for experimental purpose, with which detailed stress can be measured after FOWLP processes including mold-lst FOWLP process and RDL-1st FOWLP process. The advantages of these stress data are: (1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and (2) are important to enhance survivability during wafer process, thin-wafer handling and packaging.