Solutions for Advanced Heterogeneous Integrtion and Fan-Out Processes

Abstract

High-Performance Computing systems can employ leading-edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More-than-Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory), split-die FPGA (Field-Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting $0.8 \mu \mathrm{m}$ design rules. High-resolution lithography is required for high-density, fine-RDL applications and the main lithography challenge is to provide a large Depth-of-Focus (DoF) to reliably pattern sub-micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub-micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper). To meet the high-resolution requirements of fine-RDL processes, Canon developed the FPA-5520iV-HR [20iV-HR] i-line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High-density FOWLP wafers can also display extreme die-shift, warpage and topography that must be addressed to enable high-yield and high-productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid-PA system that automatically corrects the wafer loading position based on die-grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra-field magnification errors on a die-by-die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front-End-Of-the-Line (FEOL) stepper platform that offers die-by-die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine-RDL processes details of stepper technology that helps enable high-density integration in mass-production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine-RDL processes.