The challenge of Fan-out WLP in different process flow

Abstract

Consumer products of marketing to apply on portability and multifunction requirements to force package assembly capability improving to meet small size, high performance, and cost reduce. So Wafer Level Package (WLP) has the advantage of reducing the size of the package to meet the marketing trend of electronic products.The traditional WLP package is to arrange the bumps in the area of the wafer, in the area of the wafer by the I/O points of the wafer via the Fan-In technique, which is simply concept as Fan-In WLP. However, before deciding whether a wafer can be fabricated to use for Fan-In technology, the related factors, such as die size, number of I/O contact points, and die pad pitch, all of the factors must be evaluated to determine if the wafer has enough space to accommodate for the all points to connect.Rapid advances in front-end IC manufacturing technology bring great challenges to traditional Fan-In WLP by semiconductor scaling technology and multi-function increased, so the industry has started to develop on Fan-Out WLP that can solve the challenges of traditional WLP assembly as above mentioned.In Fan-out WLP this technique, it means reconstituted the dies and build up RDL (Redistribution Layer) to fan out and increase I/O contact points to keep small scaling package size. To achieve this concept, industry developed with two process categories: one is called Chip-First and the other is called Chip-Last. Chip-First is a process whereby the dies are attached to a temporary or permanent material structure prior to making the RDL and that will extend from the dies to ball interface. In Chip-Last process, RDL is created first and then the die will be mounted after RDL process. We would do comparing in the two different Fan-out WLP processes details. The difference will face the challenges and realize the development of Fan-out WLP process required to focus on which found mentor study.