CHAPTER 9 - Interrupt Behavior

Abstract

This chapter discusses the process of Interrupt/Exception Sequences, which include stacking, vector fetch by the instruction bus, and update of the stack pointer, link register, and program counter. It discusses nested interrupt support, which is built into the Cortex-M3 processor core and the Nested Vectored Interrupt Controller. Interrupt latency, which refers to the delay from the start of the interrupt request to the start of interrupt handler execution, is explained. The Cortex-M3 uses a number of methods to improve interrupt latency, including tail chaining and late arrival exception handling. The chapter explores the special value called EXC_RETURN, which, when loaded into the PC at the end of the exception handler execution, will cause the processor to perform an exception return sequence. Various faults can be caused by exception handling. If a bus fault takes place during stacking or unstacking, the respective sequence will be terminated and the bus fault exception will be triggered or pended. On the other hand, if a bus fault or memory management fault takes place during a vector fetch, the hard fault handler will be executed. If the EXC_RETURN number is invalid or does not match the state of the processor, it will trigger the usage fault.