CHAPTER 12 - Advanced Programming Features and System Behavior

Abstract

This chapter explores the possibilities of running a system with two separate stacks, double-word stack alignment, and the Non-base Thread Enable bit in the Nested Vectored Interrupt Controller (NVIC) Configuration Control register. If the optional Memory Protection Unit is implemented, it could be used to block user applications from accessing kernel stack memory so that they cannot crash the kernel by memory corruption. In applications that conform to the Procedure Call Standard for the ARM Architecture, it is necessary to ensure that the stack pointer value at function entry should be aligned to the double word address. To achieve this requirement, the stacking address of registers at exception handling is adjusted accordingly. A few aspects for getting the best out of the Cortex-M3 and a few tricks to speed up parts of the program while using assembly are discussed. Lockup situations in case of faults are explained. It is important to take extra care to prevent lockup problems when developing a non-maskable interrupt (NMI) or hard fault handler. FAULTMASK, used to escalate a configurable fault handler to hard fault level without the need to invoke hard fault by a real fault, is also explained.