CHAPTER 16 - Debugging Components

Abstract

This chapter focuses on a number of debugging components used to provide debugging features such as breakpoint, watchpoint, Flash Patch, and trace that the Cortex™-M3 processor comes with, all of which can be programmed through the Cortex-M3 Private Peripheral Bus. The chapter discusses the trace system that is based on CoreSight architecture—the Data Watchpoint and Trace (DWT) components and their debugging functionalities; the Instrumentation Trace Macrocell (ITM), a control register for controlling the enabling of individual features; the hardware trace with ITM and DWT; and the Embedded Trace Macrocell that is used for providing instruction traces. The chapter describes other trace components as well, which include the Trace Port Interface Unit and the Flash Patch and Breakpoint unit. It explains the Advanced High-Performance Bus Access Port (AHB-AP), a bridge between the debug interface module and the Cortex-M3 memory system, exploring three registers in the AHB-AP—the CSW register that can control the transfers, the TAR register that is used to specify the transfer address, and the DRW register that is used to carry out the data transfer operation. The ROM table, used to allow auto detection of debug components inside a Cortex-M3 chip, is also explored.