Chapter 9 - Interrupt Behavior

Abstract

This chapter discusses the interrupt support inbuilt into the Cortex-M3 processor core and the Nested Vectored Interrupt Controller (NVIC). The sequences of interrupts consist of three phases: stacking, vector fetch, and update of the stack pointer. When an exception takes place, the registers PC, PSR, R0–R3, R12, and LR are pushed to the stack. If the code that is running uses the PSP, the process stack will be used; if the code that is running uses the MSP, the main stack will be used. Afterward, the main stack will always be used during the handler, so all nested interrupts will use the main stack. While the data bus is busy stacking the registers, the instruction bus carries out another important task of the interrupt sequence: It fetches the exception vector (the starting address of the exception handler) from the vector table. Since the stacking and vector fetch are performed on separate bus interfaces, they can be carried out at the same time. After the stacking and vector fetch are completed, the exception vector will start to execute. On entry of the exception handler, a number of registers will be updated such as stack pointer. Furthermore, various faults can be caused by exception handling; for instance, if a bus fault takes place during stacking, the stacking sequence will be terminated and the bus fault exception will be triggered or pended. If the bus fault is disabled, the hard fault hander will be executed. Otherwise, if the bus fault handler has a higher priority than the original exception, the bus fault handler will be executed; if not, it will be pended until the original exception is completed.