Abstract
This chapter presents a discussion on design methodologies and computer-aided design (CAD) tool flows for networks on chips (NoCs). Designing networks on NoCs is a complex process and spans several abstraction levels—ranging from the transaction to the physical levels. Design choices are difficult to make because most figures of merit of the network depend highly on high-level decisions on architectures and protocols. Potential design closure issues require designers to explore various configurations with different parameters in the search for those that satisfy the network and overall system specifications. CAD tools are therefore very useful to shorten the design time and provide design closure. As the problem of designing the NoC involves several steps and each step requires different models of the system, a layered design flow is adopted. At the top most layer of the flow, the communication characteristics of the application are abstracted by high-level models. At this layer, based on the size and witching activity of the various NoC components, analytical models are used to characterize the power consumption of the NoC. The performance of the NoC in this layer is typically modeled by two parameters: bandwidth and hop-delay for communication. The bandwidth available across a NoC link reflects the average traffic rate that can be sustained by the link. The hop-delay metric reflects the average latency for communication in the NoC under zero-load conditions.
Published Version
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