Abstract

This chapter discusses some of the algorithms designed to implement the two-dimensional discrete cosine transform (DCT). The most prominent property is the separability property, which is exploited both in the algorithms and in the chip designs. The two-dimensional DCT can be implemented by reducing it to a lexicographically ordered one-dimensional transform that is partly recursive. More efficient algorithms result when the two-dimensional DCT is block decomposed and computations are carried out via the two-dimensional DFT. The chapter describes some hardware implementations of the two-dimensional DCT. These are representative of what active research groups are doing in the chip design area. The list, however, is not meant to be either complete or exhaustive. It is safe to say that there will be great advances in this direction, given the technological changes in the area of digital devices. Describing the fast algorithms for efficient implementation of one-dimensional and two-dimensional DCT, it is only logical to compare the performance of DCT with other discrete transforms based on some standard criteria.

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