Chapter 10 - Verification and Security Issues in On-Chip Communication Architecture Design

Abstract

Regarding on-chip communication architecture verification, this chapter focuses on two major aspects: verifying the on-chip communication architecture specification and implementations, and verifying whether IP (intellectual property) cores are compliant with the on-chip communication protocol to which they will be connected in an system-on-chip (SoC) design. In the first case, research efforts that have formally modeled several on-chip communication architecture specifications from informally specified, natural language documents found a few cases where the specification document was ambiguous, inconsistent, and incomplete. In the second case, several research efforts have proposed techniques to test if IP cores are compliant with on-chip communication protocols that are used in an SoC integration environment. This chapter also presents the motivation and fundamental concepts for secure SoC architectures, communication architecture enhancements for improving SoC security, security support in standard bus protocols, and many more.