Chapter 3 - On-Chip Communication Architecture Standards

Abstract

System-on-chip (SoC) designs typically have several different types of components such as processors, memories, custom hardware, peripherals, and external interface IP (intellectual property) blocks that need to communicate with each other. This chapter presents the prevailing standards for on-chip communication architectures. Standards are essential to promote IP reuse and reduce the design time of the increasingly complex SoC designs today. On-chip bus-based communication architecture standards define the interface signals for components, as well as bus logic components, such as arbiters, decoders, and bridges that are required to implement the features of the proposed standard. This chapter highlights some of the popular on-chip bus architecture standards, such as ARM's AMBA 2.0 and 3.0, IBM's Core Connect, ST Microelectronics' ST Bus, Sonics SMART Interconnect, Open Cores Wishbone, and Alteras Avalon. Finally, it covers popular off-chip buses and standards.