Chapter 1 - Introduction

Abstract

This chapter provides an overview of various aspects of on-chip communication in multiprocessor system-on-chips (MPSoCs), and gives an insight into why on-chip communication architectures are becoming a critical issue in MPSoC designs. There are several strategies that have been developed to cope with the SoC design complexity widening designer productivity gap. The chapter outlines two major strategies. The first is the elevation of the design process for architects to the electronic system level (ESL), where early design decisions, exploration, and platform decisions are made above the traditional logic/register transfer level (RTL). The second is aggressive exploitation of design reuse at the ESL. The reuse factor can be enhanced by increasing the granularity of library elements from standard cells to hardware (e.g., custom accelerator) and software (e.g., processor core) IP blocks. The chapter also explains ESL design flow and on-chip communication architectures.