Analysis of modified P-I-N tunnel FET architecture for applications in low power domain

Abstract

Tunnel FET with a few modifications is studied here for use in low power VLSI circuits as a worthy replacement of MOS based devices. The conventional TFET structure with P-I-N architecture is modified in the present work with dual gates, front and back, to give better control over the tunnelling current passing through the channel. In the proposed architecture asymmetrical lengths are utilised for the back and front gates, which improves the control even further. An SiGe based highly doped P + pocket is inserted in the intrinsic channel near the source end to rise the ON current and to increase the ION/IOFF ratio. In this device low subthreshold slope (SS) and lower DIBL values are also observed. The oxide layer below both the gates are engineered to optimise the combination of high and low k dielectric, lengths, to obtain performance improvement. Device Simulation Tool Silvaco Atlas is used to design and simulate the proposed device. Optimisation is done for the device with regards to length of channel, dimensions of the channel pocket, underlap and overlap lengths of the gates. The device is also tested over a wide range of temperatures to come to the best possible architecture, which is described here. The proposed device is proven to be a worthy contender to replace MOSFET in future ultra-low power, CMOS compatible VLSI circuits.