Design of Energy Efficient Ring Oscillator and Full Adder Circuit using Compact Model of MoS2 Channel TFET

Abstract

Ring oscillator and full adder circuits are ubiquitous in electronic or physical systems such as RF frequency, communication, and digital electronic systems. This paper presents the design of an inverter, ring oscillator, and full adder circuits using compact models of molybdenum disulfide (MOS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) channel-based dual-gate tunnel field-effect transistor (TFET). The TFET shows a low subthreshold slope (< 60 mV/decade) and a high on/off current ratio (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ), which are highly preferred to design low-power VLSI circuits. The performance of the designed inverter, ring oscillator, and full adder is analyzed by extracting its different parameters, such as DC transfer characteristic, power consumption, delay, and power delay product. The results show the inverter has a delay of 145ps, the ring oscillator consumes a low power of 1.92, W and its operating frequency is 31.6 GHz. The full adder designed in MOS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> TFET technology demonstrates the lowest EDP owing to its negligible static power. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuits.