Pocketed dual metal gate TFET: Design and simulation

Abstract

In this work, design and simulation of two novel tunnel field effect transistors with improved DC and radio frequency (RF) performance has been conducted. The first proposed tunnel field effect transistor (TFET) employs a highly doped n + pocket in the intrinsic channel along with a combination of stacked oxide (silicon dioxide and hafnium oxide). This configuration helps in the enhancement of tunneling at the source/channel junction, thereby improving parameters like ON-current (ION), average subthreshold slope (SS avg) and ION/IOFF. The structure is modified further by employing a dual metal gate, having different work-functions, in addition to dual stacked oxide. The gate near the source, called as the tunneling gate, has a work function of 4.3 eV and a gate near the drain side, called as the auxiliary gate, has a work-function of 4.7 eV. This second proposed structure with dual metal gate and dual oxide offers significantly improved performance with on-current (ION) of ∼3 orders more than the conventional Double Gate (DG) Tunnel FET and a sub-threshold slope of 31 mV/dec. An ION of 2.7 × 10−5 A/ µm and an OFF current (IOFF) of ∼10−16 A/ µm is achieved in the second proposed device. The AC analysis has revealed that the cutoff frequency (fT) of the second proposed device is 1055 × higher than the conventional DG-TFET. Further, an increase of 3 orders of magnitude is achieved in the gain-bandwidth (GBW) product in the second proposed device in comparison to the conventional DG-TFET.