Abstract
The most promising SRAM cells capable of operating over a wide range of supply voltages contain single-ended read ports. These systems require an external reference voltage that suitably scales to enable error-free operation of the memory, as the supply voltage is scaled. This paper presents a replica-based reference-generation technique for wide voltage range SRAMs. The proposed approach tracks the memory over the large range of supply voltages, and is tunable to extend functionality down to subthreshold voltages. In addition, a tunable delay-based timing-generation scheme is employed to enable memory functionality, in the presence of increased variation at subthreshold voltages. Configuration bits are set using a random-sampling-based Built-in Self-Test algorithm that significantly speeds up the tuning process. A 4-kb array, using the conventional 8T cell, implemented in the UMC 130-nm process, is demonstrated to function from 1.2 V down to 310 mV (at 1.3 MHz and 6.45 pJ/access). The memory consumes 0.115 pJ/bit/access at the energy optimum point of 400 mV.
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