A predischarged bitline 1T-1C DRAM readout scheme

Abstract

It is well known that the dynamic random-access memory (DRAM) is one of the main means for primary storage. However, the conventional readout scheme of the one-transistor one-capacitor (1T-1C) DRAM cells requires dealing with the relatively large bitline parasitic capacitance. This causes delay and power penalties. In this paper, a novel fast readout scheme that depends on predischarging the bitline parasitic capacitance is proposed. The several circuit design issues of the proposed scheme is analyzed quantitatively. The proposed scheme is simulated adopting the 45 nm CMOS Berkeley predictive-technology model (BPTM) with a power-supply voltage, VDD, equal to 1 V and shows 48% and 13% reductions in the read-cycle times in cases of reading “0” and “1”, respectively. The power consumption is investigated and compared with that of the conventional readout scheme taking into account the probabilities of occurrences of “0” and “1” storage.