Abstract
The one-transistor one-capacitor (1T −1C) memory cell is considered the industry standard in dynamic random-access memories (DRAMs) due to its low cost and high packing density. The main challenge associated with this type of memories is the relatively large read-access time due to the need to deal with the relatively large parasitic capacitance of the bitline. In this paper, a novel fast readout scheme is proposed in the current domain. The proposed scheme is verified by simulation adopting the 45 nm CMOS Berkeley predictive-technology model (BPTM). The average read-access time is 30% smaller than that of the conventional readout.
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