Characterization of data retention faults in DRAM devices

Abstract

Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell's ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults. I. INTRODUCTION Several recent studies (1)-(3) provide strong evidence that DRAM errors are dominated by hard errors, rather than soft er- rors, highlighting how most of these errors occur in the form of intermittent errors on the same physical address. These errors belong to the hard errors category but display characteristics that are very similar to soft errors: they are repeatable like hard errors but occurring randomly over time or only under specific conditions. According to Avi˘ taxonomy (4) (Figure 1), we can relate these errors to elusive faults: they are intricate enough that their activation conditions depend on complex combinations of internal state and external requests that occur rarely and can be very difficult to reproduce. Smart Technologies (5) stated that 95% of single bit errors reported by customers fall into the high temperature category. As the higher the temperature the quicker the memory cells charge leaks out, these errors could be related to charge storage issues: defect in the DRAM cell leads to an abnormal leakage current that discharges the cell of its stored value. Most of the writes and reads to this weak cell will proceed without error but, under special conditions, the read cycle will produce an error. DRAMs are widely used in mass memory units for space applications (6); space applications have particularly high reliability requirements therefore emerging reliability issues are quite important in this field. A specific case study triggered this work on weak cells in DRAM mass memories: during the tests performed on an ESA satellite mission several errors were detected on the SDRAM memory modules of the mass