Low-power and high-speed DRAM readout scheme

Abstract

The conventional readout scheme of the one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells depends on precharging the bitline parasitic capacitance, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL</sub> , to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> /2. Then, depending upon the stored data, this capacitance will either be charged to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> or discharged to 0 V for stored “1” and “0”, respectively. However, the bitline parasitic capacitance is relatively large (typically 250 fF for the 0.13 μm CMOS technology), thus consuming a relatively large dynamic-power consumption and causing a sluggish operation. In this paper, a novel readout scheme that doesn't require the precharge of the bitline will be proposed. Instead, the proposed scheme depends on predischarging it. The proposed scheme is simulated for the 0.13 μm CMOS technology with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.2 V and shows 50% and 75% reductions in the read cycle time in case of stored “1” and “0”, respectively. Assuming that stored “1” and “0” have the same probability of occurrence, about 60% of the dynamic-power consumption is saved.