Reading DRAM cells using two properly designed cascaded inverters

Abstract

During the reading of one-transistor one-capacitor dynamic random-access memory (1T–1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier. The net result is that the higher voltage will rise to VDD while the lower one will decrease to 0 V. Simulation results for the 0.13 μm CMOS technology reveals that approximately 40 % of the read access time is associated with the sense-amplifier operation in addition to the area required by each sense amplifier for each column in the memory array due to the need to raise or lower the relatively large bitline parasitic capacitance. Also, this process consumes relatively large amount of power. In this paper, a novel readout technique for reading DRAM cells using two cascaded inverters is proposed. Simulation using the 0.13 μm CMOS technology with VDD=1.2 V reveals that 37 % of the read access time using the conventional sense-amplifier reading scheme is saved for stored “1” which has a longer access time compared to stored “0”.