Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.

Hyeonjeong Kim,Seongjae Cho,Wookyung Sun,Songyi Yoo,Hyungsoon Shin,In-Man Kang

doi:10.3390/mi11020228

Hyeonjeong Kim, Seongjae Cho + Show 4 more

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https://doi.org/10.3390/mi11020228

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Abstract

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

Highlights

Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) has reached its scaling limit due to the difficulty of miniaturizing capacitors
Poly-Si 1T-DRAM has gained much attention [15–20]. This type of device stores its charge in its grain boundary (GB) instead of in the floating body (FB), and it is advantageous for short channel devices; its charge can be stored in the GB even with a thin body
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Summary

Introduction

Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) has reached its scaling limit due to the difficulty of miniaturizing capacitors. 1T-DRAM can be densely integrated because it has a small 4F2 cell size with a silicon-on-insulator (SOI) transistor as its basic structure. Its memory performance deteriorates with decreased transistor size. 1T-DRAM is expensive because it requires the use of an SOI wafer.

Results

Conclusion