A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure

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In this work, a 1-transistor (1T) dynamic random access memory (DRAM) cell based on a tunnel field-effect transistor (TFET) is introduced and its operation physics demonstrated. It is structurally based on a pillar structure and surrounding gate, which gives a high scalability compared with the conventional 1T-1 capacitor (1C) DRAM cell so it can be easily made into a 4F2 cell array. The program operation is performed not by hole generation through impact ionization or gate-induced drain leakage but by hole injection from the source region unlike other 1T DRAM cells. In addition, the tunneling current mechanism of the device gives low power consumption DRAM operation and good retention characteristics to the proposed device.