Abstract
Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.
Highlights
A conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cell that requires a 30 fF/cell capacitance for stable memory operation faces severe difficulties in capacitor fabrication as the transistor feature size continues to shrink [1]
The sensing margin of a silicon 1T-DRAM is significantly reduced in a thin-body device, while in a poly-Si 1T-DRAM cell there is a low body thickness effect [14]
We propose an approach to optimize short-channel poly-Si 1T-DRAM cells using device simulations with different body thicknesses and Write“1” drain voltages
Summary
A conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cell that requires a 30 fF/cell capacitance for stable memory operation faces severe difficulties in capacitor fabrication as the transistor feature size continues to shrink [1]. Capacitorless 1T-DRAM cells, which consist of only one silicon-on-insulator (SOI) transistor without the complications of capacitor manufacturing, have attracted attention as replacements [2,3]. 4 F2 cell size; it distinguishes its data by using a floating body (FB) as a charge storage region [4,5,6,7,8]. It cannot operate in a fully depleted silicon-on-insulator (FD-SOI) device because there is no FB region to store charge. The sensing margin of a silicon 1T-DRAM is significantly reduced in a thin-body device, while in a poly-Si 1T-DRAM cell there is a low body thickness effect [14]
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