Capacitorless one-transistor dynamic random access memory based on double-gate GaAs junctionless transistor

Abstract

In this paper, we present a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a double-gate GaAs junctionless transistor (JLT). The proposed 1T-DRAM exhibits an excellent reading operation with a large sensing margin between the “1” and “0” states because the excess hole charges effectively screen the electric field formed by the gate2 voltage (VGS2). In order to reduce the electric field in the drain–gate interface involved in recombination, HfO2 is used as the spacer dielectric. The 1T-DRAM obtains a long retention time of 71 ms due to a low recombination rate. Moreover, we investigate the effect of geometric parameters on DRAM characteristics. The gate length (LG) and body thickness (Tbody) have a major impact on the sensing margin and retention time. The 1T-DRAM with a long LG and a thin Tbody can operate with a low power (LP) consumption, a long retention time, and high-density integration.