A Novel Charge-Sharing based DRAM Readout Scheme

Abstract

During the readout of the one-transistor one-capacitor dynamic-random-access memories (1T-1C DRAMs), the need arises to deal with the relatively large parasitic capacitance of the bitline. In this paper, a novel fast readout scheme is proposed that depends on charge sharing between the bitline-parasitic capacitance and another properly sized capacitor. The 45 nm CMOS Berkeley predictive-technology model (BPTM) is used in verifying the proposed readout scheme. According to the simulation results, approximately 25% of the average read-access time is saved.