A Novel Scan Architecture for Low Power Scan-Based Testing

Mahshid Mojtabavi Naeini,Chia Yee Ooi

doi:10.1155/2015/264071

Abstract

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

Highlights

Nowadays, design-for-testability (DFT) techniques have become an inseparable consideration for testing modern microelectronic designs as they play an important role in the improvement of the test quality and reducing the test application time in the VLSI digital circuits
Since there is less correlation among scan test patterns generated by an Automatic Test Pattern Generation (ATPG) tool compared to the data during normal mode, high switching activities incurred in capture mode have increased test power drastically over chip power limitations
first level supply (FLS) scheme has less overhead in terms of area, propagation delay, or even switching activity in gating logic compared with other gating schemes, it is unable to block all transients in the combinational logic because the output of the first level gates is forced to a fixed value, which is similar to NOR and TG gating

Summary

Introduction

Design-for-testability (DFT) techniques have become an inseparable consideration for testing modern microelectronic designs as they play an important role in the improvement of the test quality and reducing the test application time in the VLSI digital circuits. Excessive average power affects not VLSI Design only temperature increase and temperature variations These temperature variations may induce timing variations during test and, in some cases, may lead to test-induced yield loss [3]. As pointed in [3, 4], excessive peak power dissipation comes with a high instantaneous current demand due to high switching activity during test application time which may cause power supply noise (PSN). Shift power consumption is due to the transitions occurring in scan cells when the adjacent bits in test vector have different values These transitions cause switching activity in scan cells but they are propagated to the combinational logic through scan cells outputs.

Previous Works

The Proposed Gating Scan Architecture

Experimental Results and Comparisons

Conclusion