Abstract
Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology.
Highlights
The most major concerns regarding challenges to test current high integration density circuits are the test cost and test power
Since there is less correlation between scan test vectors generated by an Automatic Test Pattern Generation (ATPG) tool compared to the data during normal mode, high switching activities incurred in capture mode have increased the test power drastically over the chip power threshold
Significant delay on signal propagation paths, large area overhead, high switching activity, and undesired impacts on peak power all caused by gating logics, has made them less practical for large industrial circuits
Summary
The most major concerns regarding challenges to test current high integration density circuits are the test cost and test power. A novel low power gating scan cell for shift power reduction considering both the scan chain and combinational part with the following features is presented:. The proposed gating scan architecture introduces a new short shift path that improves both shift and capture propagation delays as well as power consumption in the scan chain during shift mode. This makes shifting at higher frequency possible in those cases where the maximum shift frequency has been bounded by the maximum allowable power consumption. The proposed structure contributes to the average power reduction in the scan architecture (combinational logic and scan chain) during shift mode while not causing high peak power during capture mode.
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