VLSI implementation of low power scan based testing

Abstract

Power consumption in test becomes a higher barrier for consideration in test of any combinational circuit is high during test mode as in its normal mode of functioning as enormous power dissipation seriously affects the chip reliability. Many techniques are proposed to lower down the test power. In scan based design, rippling transition created by test patterns shifting along the scan chain not only rises power loss but also offers spurious switching activities in the combinational circuits or logic. This paper propose a novel scan cell architecture for low power scan based technique with power-efficiency that provides combined solution for reducing total average power in both combinational part and scan cell during capture mode and shift mode. The proposed scan cell reduces the number of transitions during shift and capture mode. The proposed method is implemented on the different combinational Tanner circuits and the experimental results were observed. Simulation results have shown that the proposed gating scan cell save 20∼25% total average power in shift and capture mode as compared to conventional scan cell.