A novel LDO circuit with high-speed current detection

Abstract

Abstract This paper proposes a Low Dropout Regulator (LDO) circuit with high-speed current detection. The current detection circuit utilizes a latch-based structure to expedite comparisons and perform detection. Its primary objective is overcurrent protection in certain practical applications, achieving current limit functionality. The LDO circuit structure can stably provide a 5 V output voltage under a 9 V input voltage, with a maximum output current limit of 70 mA. In practical applications, the circuit can function with a load current of 40 mA, resulting in an output voltage (Vout) of 4.96 V. In the design of the LDO circuit, the Error Amplifier (EA) module departs from conventional internal structures, employing a dual-potential folded cascode common-gate common-source amplifier. This choice enhances parameters such as EA gain and Power Supply Rejection Ratio (PSRR). The gain achieves 98 dB, and the low-frequency PSR reaches 92 dB. Simultaneously, the dual potential configuration significantly economizes the layout area required in practical implementations. The LDO is designed using a 0.18 μm standard CMOS process.