Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator

Abstract

An easy-to-use efficient auto-design approach to achieve a synchronous optimization and solution for multiple performance objectives of a CMOS low-dropout regulator (LDO) circuit is proposed. As a core algorithm, response surface methodology (RSM) is adopted to automatically implement the design parameter modeling and solving of the LDO. The precision response surface models for the temperature coefficient (TC) and power supply rejection ratio (PSRR) are established efficiently based on only 27 sets of Cadence sampling datasets, by which the optimal performance solution with a superior tradeoff on TC and PSRR can be obtained. Along with a complete auto-design flow, the pre/post-layout simulations of the LDO circuit by SMIC 180 nm/3.3 V CMOS technology are performed, it can be observed that the auto-improved LDO has a significant better 35.20 ppm/°C TC feature compared with 48.46 ppm/°C that recorded by the manual design. Synchronously, the PSRR is improved from −59.497 Hz@DC to −92.89 Hz@DC with a great increase ratio by 56 % up.