Abstract
In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.
Highlights
In the power management system, the demand for integrating the whole power management integrated circuit (PMIC) into a single chip has significantly increased [1]
Regulator is to reject the ripples from the voltage source, which means power supply rejection (PSR) is vital
We introduce an LDO regulator which achieves a significantly improved PSR by utilizing the feed-forward ripple cancellation technique
Summary
In the power management system, the demand for integrating the whole power management integrated circuit (PMIC) into a single chip has significantly increased [1]. We introduce an LDO regulator which achieves a significantly improved PSR by utilizing the feed-forward ripple cancellation technique The purpose of this technique is to duplicate the input ripples to the gate of the pass transistor so that it will cancel out the input ripples to increase. A conventional LDO regulator, shown, includes a pass transistor M and an error amplifier for comparing the voltage of the feedback circuit and Vref.
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