Abstract
A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.
Highlights
With recent CMOS technologies, the device sizes are scaled down while the computational speed of the VLSI system is increased
We propose an alternative full-duplex transceiver (FDT)
The results show that the proposed solution can offer the highest data rate of 16 Gbps among the other designs with competitive power consumption
Summary
With recent CMOS technologies, the device sizes are scaled down while the computational speed of the VLSI system is increased. Several unidirectional signaling solutions have been reported to achieve energy-efficient high data rates over on-chip interconnects [4,5,6]. High data rates can be achieved at the cost of increased chip area and power consumption for bidirectional signaling. Thereinafter, a simultaneous bidirectional transmission scheme has been presented for synchronous data at the two ends of the interconnect achieving a data rate of less than 2 Gbps with increased power consumption [30]. A wide channel has been used which is not too much lossy Another hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects have been proposed in [33]. A high-speed power-efficient transceiver is proposed for full-duplex signaling over on-chip interconnects.
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