An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects

Abstract

Full-duplex communication over on-chip interconnects requires a hybrid circuit that separates the inbound signal from the superimposed signal by subtracting the outbound signal. This operation results in an echo and incomplete cancellation of this echo leads to residue. Non-zero residue reduces the amplitude and timing margins in the recovered signal eye-diagram. This work for the very first time proposes an adaptive transceiver for near zero-residue for full-duplex communication over on-chip interconnects by deploying a residue monitor. The proposed hybrid circuit topology employs low power chargemode integrated circuits compared to traditional high power consuming current-mode and voltage-mode echo-cancellation circuits. In the proposed scheme, the operation of cancelling the outbound signal is assisted by a replica generation stage which replicates the outbound signal in terms of signal swing is realized by the digitally re-configurable capacitor-bank. The echo-cancellation is implemented at the circuit level in 1.2V, 65 nm CMOS over a 1-mm on-chip interconnect and the residue monitor architecture is realized with behavioural modeling in Verilog-AMS. The proposed scheme operates at a data rate of 10-Gb/s with a total power consumption of 9.64 mW. The loop locks for a control voltage of 173 mV with an adaptation time of 5.74 ns and the corresponding swing of the replica signal is 230.13 mV with a final residue of only 3.13 mV. The extracted inbound signal has a differential swing of 154 mV.