Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects

Abstract

In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .