18 - Design Optimization Example: DES

Abstract

This chapter explores Data Encryption Standard (DES). The use of behavioral synthesis is investigated as an alternative to create optimal designs rather than using a Register Transfer Logic (RTL) approach. The chapter describes the experience of designing a DES core in an Electronic Code Book (ECB) mode using the Multiple Objective Optimization in Control and Datapath Synthesis (MOODS) behavioral synthesis system. The main objective is to write a high-level language description that is both readable and synthesizable. The other objective is to explore the area/delay design space of both single and triple DES. The designs are simulated using both the pre-synthesis and post-synthesis VHSIC hardware description language (VHDL), where VHSIC stands for very high speed integrated circuit. It is possible to design complex algorithms such as DES using the abstraction of high-level VHDL and get a synthesizable design. However, the synthesis process is not and cannot ever be fully automated. Thus, human guidance is still necessary to optimize the design's structure to get the best from the synthesis tools. Nevertheless the modifications are high-level design decisions and the final design is still readable and abstract.